1. Field of Invention
The present invention relates to a voltage regulator, and a control circuit and a method for controlling the voltage regulator, in particular to such voltage regulator, control circuit and method wherein a compensation signal is generated to adjust the output voltage of the voltage regulator according to a dynamic voltage identification (DVID) signal.
2. Description of Related Art
The major concept of dynamic voltage adjustment is to supply a variable operation voltage to the system. When the system needs to process data in high speed, the voltage is increased to a higher level to enhance the processing speed of a digital signal processor or a microprocessor. When the system does not need to process data in high speed or it is in a stand-by mode, the voltage is decreased to a lower level by an instruction from the system, such that unnecessary power consumption can be saved. Thus, it is required for a voltage regulator supplying the operation voltage to the system to be able to quickly adjust its output voltage so as to meet the requirement from the processor.
FIG. 1 shows a prior art voltage regulator supplying a dynamic voltage to a processor. The voltage regulator 10 comprises a control circuit 12 and a power stage 14. The control circuit 12 controls the power stage 14. The power stage 14 includes two power transistors (Q1, Q2) and an inductor L. The control circuit 12 generates control signals to control the operations of the transistors (Q1, Q2) according to the output voltage Vout or a feedback signal FB extracted from the output side Vout by a feedback circuit 20, an inductor current IL through the inductor L, and a DVID signal instructed by a CPU (Central Processing Unit) 11, so as to transmit electrical power from the input side Vin to the output side Vout. The inductor current IL through the inductor L charges a capacitor C. The voltage across the capacitor C is the output voltage Vout at the output side. The load current ILOAD is outputted from the output side and supplied to the CPU 11.
The specification of the DVID signal is defined by Intel in its specification of the voltage regulator module (VRM), which includes instructions for various voltages and corresponding slew rates. For example, the CPU 11 sends a DVID signal to request the output voltage Vout to change from 0.5V to 0.8V by a slew rate of 10 mV/μs, and hence, the voltage regulator 10 needs to raise the output voltage Vout to 0.8V within 30 μs (=(0.8−0.5)/0.01). Intel also lists the specification of load line impedance in the specification, expressed by ΔVout/ΔILOAD. For example, the load line impedance of the voltage regulator 10 is 1 mohm, and ΔVout/ΔILOAD is possibly desired to be 1 mV/A. That is, when the output voltage Vout drops 10 mV, the load current ILOAD increases 10 A. However, the conventional voltage regulator 10 only detects the inductor current IL, but does not detect the actual load current ILOAD Because this requires disposing a power consuming device on the output path.
Referring to FIG. 2A, when the output voltage Vout of the voltage regulator 10 is at a stable status, the average of the inductor current IL is equal to the load current ILOAD, so in prior art concept, the average of the inductor current IL can represent the load current ILOAD. However, referring to FIG. 2B, when the voltage regulator 10 increases the output voltage Vout from 0.5V to 0.8V in response to the DVID signal from the CPU 11, it increases the inductor current IL to be larger than the load current ILOAD so as to charge the capacitor C with extra current, such that the output voltage Vout can be raised to a desired target. Meanwhile, the voltage regulator 10 detects the rising inductor current IL, so it mistakes the load current ILOAD to be increasing at the same speed as the increase of the inductor current IL. However, according to the requirement of the load line impedance, the actual output voltage Vout unexpectedly drops (referred to as “droop”). Consequently, the actual output voltage Vout delays its response to reach a higher level, that is, it gets to the target voltage 0.8V later than the expected time point, so it cannot meet the slew rate requirement in specification of the DVID signal. On the contrary, if the desired output voltage Vout needs to drop to 0.5V from 0.8V, an unexpected negative droop or boost occurs in the actual output voltage, and there is a similar delay in the response time of the actual voltage Vout. Even though the load line impedance of the voltage regulator is assumed to be zero, because of the finite bandwidth of the feedback loop in the circuit, the response of the output voltage Vout is still delayed.
In view of above, the present invention overcomes the foregoing drawbacks by providing a voltage regulator and a control circuit and a method, wherein a compensation signal is generated to adjust the output voltage of the voltage regulator according to a dynamic voltage identification (DVID) signal. Consequently, the response time of the actual voltage Vout is improved to solve the problem of the delayed response due to the droop or negative droop.